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Sr. Engineer, Verifications
SiTime Corporation
Rijswijk · PresencialSênior (5–10 anos)Tempo integralPublicada há 14 dias
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O que você vai fazer
The Senior Verification Engineer will develop UVM-based verification environments and SV-RNM models for MEMS timing ICs. Responsibilities include defining verification plans, running simulations, debugging results, and collaborating with cross-functional teams for tape-out sign-off.
O que eles procuram
Candidates must hold a degree in electrical or computer engineering with at least 5 to 8 years of relevant semiconductor verification experience. Proficiency in SystemVerilog, UVM, and scripting languages like Perl or Python is required, along with strong communication skills.
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