Todas as vagas
Design Verification Engineer
Amsterdam · PresencialSênior (5–10 anos)Tempo integralPublicada em 17 de ago. de 2026
Sobre a vaga
O que você vai fazer
Develop and execute verification strategies for complex FPGA and ASIC RTL designs while maintaining automated test suites. Collaborate with design, architecture, and software teams to identify, debug, and document functional issues.
O que eles procuram
Requires 5+ years of experience in RTL functional verification for FPGA or ASIC designs. Candidates must possess advanced knowledge of SystemVerilog and UVM, along with hands-on experience using verification EDA tools.
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