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Design Verification Engineer
Amsterdam · On-siteSenior (5–10 years)Full-timePosted 17 Aug 2026
About the job
What you'll do
Develop and execute verification strategies for complex FPGA and ASIC RTL designs while maintaining automated test suites. Collaborate with design, architecture, and software teams to identify, debug, and document functional issues.
What they're looking for
Requires 5+ years of experience in RTL functional verification for FPGA or ASIC designs. Candidates must possess advanced knowledge of SystemVerilog and UVM, along with hands-on experience using verification EDA tools.
Full description