Todas as vagas
ASIC Digital Verification, Sr Staff Engineer
Synopsys
Eindhoven · PresencialSênior (5–10 anos)Tempo integralPublicada em 21 de jun. de 2026
Sobre a vaga
O que você vai fazer
You will design and execute verification strategies for complex security IP subsystems, including building UVM testbenches and formal verification flows. Additionally, you will collaborate with design teams to root-cause defects and ensure hardware-software integration across various platforms.
O que eles procuram
Candidates must have a Bachelor's or Master's degree in Electrical Engineering or Computer Science with at least 6 years of hands-on verification experience. You are required to have deep expertise in SystemVerilog, UVM, and formal verification techniques, along with a proven track record in silicon tape-outs.
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