Todas as vagas
ASIC Design Verification Engineer - Specs
Snap Inc.
Eindhoven · Híbrido, 4 dias no escritórioSênior (5–10 anos)Tempo integralPublicada em 5 de out. de 2026
Sobre a vaga
O que você vai fazer
Responsible for the verification of AI ASIC designs, taking ownership of complex IP blocks and subsystems for edge AI and camera IPs. The role involves driving the project lifecycle from specification to coverage sign-off and collaborating cross-functionally to refine requirements.
O que eles procuram
Requires 5+ years of experience in UVM, SystemVerilog, and coverage-driven verification with expertise in NPUs or image/video processing. Candidates must be proficient in RTL and experienced with modern CI/CD workflows and Git.
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