Todas as vagas
Sr. Engineer, Digital Design
SiTime Corporation
Rijswijk · PresencialSênior (5–10 anos)Tempo integralPublicada há 14 dias
Sobre a vaga
O que você vai fazer
Develop micro-architecture specifications and RTL designs for digital logic circuits using Verilog or SystemVerilog. Collaborate with cross-functional teams to perform synthesis, timing analysis, and post-silicon validation.
O que eles procuram
Requires a Master's degree in electrical engineering and at least 5 years of relevant industry experience. Candidates must be proficient in digital logic design, RTL flow, and scripting languages like Perl, Tcl, or Python.
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