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Digital Design Engineer
Amsterdam · PresencialSênior (5–10 anos)Tempo integralPublicada em 2 de out. de 2026
Sobre a vaga
O que você vai fazer
The Digital Design Engineer will architect, develop, and integrate RTL and IP for FPGA and ASIC-based products while ensuring performance goals are met. They will also coordinate with cross-functional teams to manage integration requirements, design reviews, and hardware bring-up.
O que eles procuram
Candidates must have 5+ years of experience in digital design and RTL development with advanced knowledge of SystemVerilog or Verilog. Proven experience in developing and integrating IP in complex SoC or FPGA-based systems is required.
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