Todas as vagas
Design Verification Engineer
Fortaegis
Amsterdam · PresencialSênior (5–10 anos)Tempo integralPublicada em 10 de jul. de 2026
Sobre a vaga
O que você vai fazer
The engineer will develop and execute verification strategies for complex FPGA and ASIC RTL designs. This includes designing verification environments and collaborating with design teams to debug and document functional issues.
O que eles procuram
Candidates need over 5 years of experience in RTL functional verification with advanced knowledge of SystemVerilog and UVM. Proficiency with EDA tools and experience in high-speed networking or cryptographic IP is highly advantageous.
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