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Design Verification Engineer
Fortaegis
Amsterdam · On-siteSenior (5–10 years)Full-timePosted 10 Jul 2026
About the job
What you'll do
The engineer will develop and execute verification strategies for complex FPGA and ASIC RTL designs. This includes designing verification environments and collaborating with design teams to debug and document functional issues.
What they're looking for
Candidates need over 5 years of experience in RTL functional verification with advanced knowledge of SystemVerilog and UVM. Proficiency with EDA tools and experience in high-speed networking or cryptographic IP is highly advantageous.
Full description